library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity registroupa is
Port ( clk : in STD_LOGIC;
boverflow : in std_LOGIC;
bsigno : in std_logic;
bcero: in std_logic;
bacarreo :in std_logic;
UPAV : out std_LOGIC;
UPAC : out std_LOGIC;
UPAN : out std_logic;
UPAZ: out std_logic);
end registroupa;

architecture Behavioral of registroupa is

begin
process (clk,boverflow,bsigno,bcero)
begin

if rising_edge (clk) then
UPAV <= boverflow;
UPAN <= bsigno;
UPAZ <= bcero;
UPAC <= bacarreo;
end if;
end process;
end Behavioral;